1. Field of the Invention
The present invention relates generally to static comparator circuits and more particularly to an integrated exclusive-nor gate and flip-flop.
2. Description of the Relevant Art
Exclusive-or (XOR) gates are often used in electronic circuits to compare the logic levels of input signals. The output of an exclusive-or gate is asserted if one, but not both, of the inputs to the exclusive-or gate are asserted. If both inputs to the exclusive-or gate are asserted or both inputs are deasserted, the output of the exclusive-or gate is deasserted. An exclusive-nor (XNOR) gate is similar to an exclusive-or gate with the output inverted. Accordingly, the output of an exclusive-nor gate is asserted if both inputs are asserted or both inputs are deasserted. An exclusive-or or an exclusive-nor gate may be used to determine whether the logic levels of two inputs are the same.
It is often desirable to perform a static comparison of two inputs. Static logic circuits are often more desirable than dynamic logic circuits. Static logic circuits are more robust with respect to noise than dynamic circuits. Additionally, in certain cases, static circuits consume less power than dynamic circuits (power consumption is pattern and implementation dependent). Static circuits are also faster in some cases, especially if the desired evaluation phase coincides with the precharge phase of a dynamic circuit.
Turning now to FIG. 1, one embodiment of a static comparator is shown. FIG. 1 illustrates a one-bit static comparator using an exclusive-nor (XNOR) gate. FIG. 1 includes flip-flop 102, flip-flop 104, and exclusive-nor gate 106. Exclusive-nor 106 includes inverters 108, 110 and 116, and transmission gates 112 and 114.
A first input of flip-flop 102 is coupled to input A. A first input of flip-flop 104 is coupled to input B. The clock inputs of flip-flops 102 and 104 are coupled to a clock signal (CLK). The outputs of flip-flops 102 and 104 are coupled to inputs of exclusive-nor gate 106. The output of exclusive-nor gate 106 is coupled to an output Z.
On a predefined edge of the clock signal flip-flops 102 and 104 latch the current state of input signals A and B respectively. A short time after the predetermined edge of the clock signal, the logic levels of inputs A and B are available at the outputs of flip-flops 102 and 104 and at the inputs of exclusive-nor gate 106. After a short delay, output Z of exclusive-nor gate 106 will be asserted if the inputs A and B are the same logic state. Alternatively, output Z will be deasserted if inputs A and B are different logic states. Because inputs A and B are captured by flip-flops 102 and 104, the circuits that drive A and B may transition after the predetermined edge of the clock without affecting the output Z.
As noted above, output Z of exclusive-nor gate 106 is asserted when either both inputs are asserted or both inputs are deasserted. Input B controls transmission gates 112 and 114. If input B is asserted, then transmission gate 114 logically couples input A to output Z. The output of inverter 108 is the inversion of input A and the output of inverter 116, which is output Z, is the same state as input signal A. Accordingly, when input B is asserted, output Z is asserted if input signal A is asserted and output Z is deasserted if input signal A is deasserted.
If input signal B is deasserted, then output signal Z is the inverse of input signal A. If input signal A is asserted, output signal Z is deasserted. Transmission gate 112 logically couples input A to the input of inverter 116 when input B is deasserted.
Although FIG. 1 illustrates a single bit comparator, a plurality of single bit comparators may be combined to compare multiple bits. In this embodiment, each pair of bits of the input signals are compared using a comparator similar to the one illustrated in FIG. 1. The outputs of each single-bit comparator may be input to an AND gate. If each pair of bits are the same logic level, then all the outputs of the comparators will be asserted. Accordingly, the output of the AND gate coupled to the comparators will also be asserted indicating that the multiple bit inputs are the same.
Turning now to FIG. 2, one embodiment of a flip-flop is shown. Flip-flop 102 includes inverters 202, 204, 210, 212, 216, 218 and 220, NAND gate 206, NOR gate 208, and transmission gate 214. In one embodiment, transmission gate 214 logically couples the output of inverter 210 to the input of inverter 220 when the output of NOR gate 208 is asserted. NOR gate 208 is asserted when both the clock input signal and the output of NAND gate 206 are deasserted. If the enable (ENB) input signal is deasserted, NAND gate 206 is asserted which prevents NOR gate 208 from enabling transmission gate 214. Thus, if the enable input signal is deasserted, transmission gate 214 is disabled. Alternatively, if the enable input signal (ENB) is asserted, the output of NAND gate 206 is deasserted when the output of inverter 204 is asserted. The output of inverter 204 is a delayed version of the clock input signal. Accordingly, when the enable input is asserted, NOR gate 208 will enable transmission gate 214 while the clock signal is deasserted and a delayed version of the clock signal is asserted. This set of conditions exists for a brief period of time on a transition of the clock signal from the asserted to the deasserted state. This brief period of time is approximately equal to the propagation delay of inverters 202 and 204 and NAND gate 206. During this brief period of time, transmission gate 214 is enabled and couples the inversion of the input to the inputs of inverters 218 and 220.
Inverters 216 and 218 comprise a keeper circuit. The keeper circuit is designed to maintain the logic level of the output of transmission gate 214 after transmission gate 214 has been disabled. When transmission gate 214 is enabled, it drives the input of inverter 218. The current drive of transmission gate 214 is sufficient to overcome the current output of inverter 216. Accordingly, if the output of transmission gate 214 is a different state than the output of inverter 216, the output of inverter 218 will be the inversion of the output of transmission gate 214, not inverter 216. The output of inverter 218 drives the input inverter 216 such that the output of inverter 216 is the same state as the output of inverter 214. After transmission gate 214 is disabled, inverters 216 and 218 maintain the logic level output by transmission gate 214 prior to being disabled. Inverter 220 inverts the state maintained by inverters 216 and 218 and buffers the output Q.
Flip-flop 104 may implement a similar or identical circuit to flip-flop 104.
Unfortunately, conventional comparison circuits such as those shown in FIGS. 1 and 2 are too slow for some applications. What is desired is a faster static comparator circuit.